Implementation of a High Speed Four Transmitter Space-Time Encoder using Field Programmable Gate Array and Parallel Digital Signal Processors

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12596722_Taylor.pdf (370.05 KB)
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Conference Contributions - Published
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http://hdl.handle.net/10092/4110
Publisher's DOI/URI
https://doi.org/10.1109/DELTA.2006.55
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University of Canterbury. Electrical and Computer Engineering
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2006
Authors
Green, P.J.
Taylor, D.P.
Abstract

This paper describes the concept, architecture, development and demonstration of a high performance, 4 transmitter, real-time space time encoder designed for research into transmitter diversity and multiple input and multiple output (MIMO)wireless systems. It is implemented on a Xilinx Virtex 2 Pro Field Programmable Gate Array (FPGA) and parallel processing on multiple Freescale DSP56321 digital signal processors (DSP). The system is software defined to allow for flexibility in the choice of transmit modulation formats, data rates and space-time coding schemes. Hardware, firmware and software aspects of the space time encoder system to meet design requirements are discussed. The testing and demonstration of the system running the Alamouti space time coding scheme is covered.

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Citation
Green, P.J., Taylor, D.P. (2006) Implementation of a High Speed Four Transmitter Space-Time Encoder using Field Programmable Gate Array and Parallel Digital Signal Processors. Kuala Lumpur, Malaysia: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 Jan 2006. Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 466-471.
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c) 2006 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
https://hdl.handle.net/10092/17651
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Engineering: Conference Contributions