Periodic Loop Structure for Combining Power FETs
| dc.contributor.author | Eccleston, K.W. | |
| dc.date.accessioned | 2009-12-22T23:16:29Z | |
| dc.date.available | 2009-12-22T23:16:29Z | |
| dc.date.issued | 2008 | en |
| dc.description | on CDROM | en |
| dc.description.abstract | Power dividers and combiners are important components in combined power amplifiers. For ease of integration with transistors (or amplifier modules) on a planar circuit, the output ports of the divider and the input ports of the combiner should be aligned in a straight line. When fork or radial power combiners are used, irregular meandering of interconnecting transmission lines is required [1]. Microstrip corporate power combiners [2] and suitably designed tapered microstrip combiners [3], on the other hand, have input ports in a straight line. Most power dividers and combiners are meant to be terminated at all ports with matched loads. When integrating with transistors, matching is required, and this adds to the circuit complexity and size. In the interests of improving integration of transistors and power combiners and dividers, a number of approaches have been developed such as the dual-fed distributed amplifier [4] and the distributed active transformer [5][6]. The power combiner needs to transform an external load (typically 50 Ω) to a suitable load impedance for the transistors which is low for power FETs. The load-impedance presented to each FET of the dual-fed distributed amplifier is proportional to the number of FETs, N, [4], and inversely proportional to N for the distributed active transformer [5]. The distributed active transformer therefore permits combining of microwave power FETs without needing additional impedance transformers. The distributed active transformer requires tightly coupled lines and implementation requires a multi-metal-layer technology. In this work we propose an N-way circuit level power combiner for FETs that achieves a 1/N impedance transformation ratio and can be implemented in a single layer microstrip technology. | en |
| dc.identifier.citation | Eccleston, K.W. (2008) Periodic Loop Structure for Combining Power FETs. Hong Kong / Macau: 2008 Asia Pacific Microwave Conference, 16-20 Dec 2008. | en |
| dc.identifier.doi | https://doi.org/10.1109/APMC.2008.4958379 | |
| dc.identifier.uri | http://hdl.handle.net/10092/3309 | |
| dc.language.iso | en | |
| dc.publisher | University of Canterbury. Electrical and Computer Engineering | en |
| dc.rights | "©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." | en |
| dc.rights.uri | https://hdl.handle.net/10092/17651 | en |
| dc.subject.marsden | Fields of Research::290000 Engineering and Technology::290900 Electrical and Electronic Engineering::290903 Other electronic engineering | en |
| dc.title | Periodic Loop Structure for Combining Power FETs | en |
| dc.type | Conference Contributions - Published |
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