Embedded digital video implementations using dynamically reconfigurable DSP.
Thesis DisciplineMechanical Engineering
Degree GrantorUniversity of Canterbury
Degree NameMaster of Engineering
The rapid growth in technology of wireless communications has cleared the way for advanced features such as real-time video applications to be included on portable handheld devices. The ISO MPEG-4 video standard is emerging as the predominant format for these applications. In order to meet the stringent low-power requirements of battery-powered devices and keep up with the ever-evolving MPEG-4 standard, the computationally costly MPEG-4 algorithms must be implemented in software with maximum efficiency. This research is devoted to the analysis of the algorithms involved with the aim of facilitating an efficient, programmable MPEG-4 solution within a 60 Mcycle budget, for implementation on a multi-core, multiapplication, 3G cellular phone. The implementation will employ 16-bit telecom DSP’s, particularly the Infineon Carmel 10xx and 20xx processors, with dynamic reconfigurability as an enabling technology on the Carmel 20xx. Through analysis of the individual algorithms, dynamic reconfigurability is shown to facilitate significant reductions in the overall computational and data-memory requirements of the MPEG-4 video codec. A reduction in computational cost of approximately 20% was demonstrated for the typical operation of fully programmable MPEG-4 simple profile at level 0, and level 1 video codecs. In addition, the memory requirements are also reduced by 33% from 344k words to 230k words. These reductions are a direct result of reconfiguring the Carmel 20xx as a highly parallel 8-bit processor using two proposed PowerPlug modules. Dynamic reconfigurability provides the performance required to enable a fully programmable, real-time, duplex MPEG-4 video application on a portable handheld device.