Thesis DisciplineElectrical Engineering
Degree GrantorUniversity of Canterbury
Degree NameDoctor of Philosophy
Efforts to downscale transistor dimensions to satisfy the demands for ultra high density integrated circuits have been met so far with optical lithography techniques. However, they are now facing their fundamental limits including optical diffraction and the limits associated with UV exposure sources. The feature size required for current integrated circuits is 45nm. In the near future it is predicted to reach 15nm node where conventional photolithography can no longer be employed. As a result, extensive research has been devoted into the development of next generation lithography processes and new transistor structures. Among the potential candidates for next generation transistor devices, nanowire based field effect structures made from a single layer of metal are proposed. These types of transistors are designed to operate similarly to a depletion type of MOSFET by governing the flow of electrons in a narrow nanowire channel. In this study, metallic nanowire structures were designed, fabricated and tested. Nanowires with diameters as small as 12.5nm were fabricated using electron beam lithography (EBL), thermal evaporation and metal lift-off process. Optimisations of EBL parameters were made to deliver wires ranging from 200nm down to 12.5nm mainly by suppressing charging effects and minimising factors that contribute to proximity effects. These structures were the first in the Nanofabrication laboratory at the University of Canterbury to be fabricated with such dimensions. Nanowire structures in Y shaped and planar gated configurations have also been tested using Ag, Al, and NiCr. Metallic nanowire devices were deposited on insulating substrates such as Si₃N₄ or SiO₂ to facilitate electrical characterisation and device operation. In the fabrication, the minimum achievable line widths is mainly determined by the surface charging effects due to the direct EBL patterning on insulating substrates and by proximity effects for having gate structures located few tens of nanometres away from the main nanowire. Electrical characterisations including two point, four point, transmission line measurements, and gate effects were performed using semiconductor parameter analyser to study the conduction and gating effect of these nanowires with gate electrodes that are separated by air gaps in the range of 20nm-200nm. The main challenging issues found to affect the characterisation results are the voltage offset problem during four point resistance measurement, the charge fluctuation and the effect of joule heating during long integration measurements. To further study the gate effects of nanowires based on semi-metals, focused ion beam (FIB) technology was employed for the fabrication of bismuth nanotransistor structures, with minimum dimensions in the 30nm scale. In addition, we have for the first time report the creation of highly ordered and multiple layers of nano dots stacking using electron beam induced metal deposition in FIB. In this thesis, although no significant gating effects were observed due to difficulties involved in further reducing the nanowire widths beyond the 12nm node, the fabrications and characterisations of these nanowire structures have allowed us to explore the resolution limits of these processes and at the same time create a platform suitable for studying the conduction characteristics, transport properties and the gate effects for nanowires made from semiconductor, metal and semimetal.