Fabrication, Characterization, and Modelling of Self-Assembled Silicon Nanostructure Vacuum Field Emission Devices
Thesis DisciplineElectrical Engineering
Degree GrantorUniversity of Canterbury
Degree NameDoctor of Philosophy
The foundation of vacuum nanoelectronics was laid as early as in 1961 when Kenneth Shoulders proposed the development of vertical field-emission micro-triodes. After years of conspicuous stagnancy in the field much interest has reemerged for the vacuum nanoelectronics in recent years. Electron field emission under high electric field from conventional and exotic nanoemitters, which have now been made possible with the use of modern day technology, has been the driving force behind this renewal of interest in vacuum nanoelectronics. In the research reported in this thesis self-assembled silicon nanostructures were studied as a potential source of field emission for vacuum nanoelectronic device applications.
Whiskerlike protruding silicon nanostructures were grown on untreated n- and p-type silicon surfaces using electron-beam annealing under high vacuum. The electrical transport characteristics of the silicon nanostructures were investigated using conductive atomic force microscopy (C-AFM). Higher electrical conductivities for the nanostructured surface compared to that for the surrounding planar silicon substrate region were observed. Non-ideal diode behaviour with high ideality factors were reported for the individual nanostructure-AFM tip Schottky nanocontacts. This demonstration, indicative of the presence of a significant field emission component in the analysed current transport phenomena was also detailed. Field emission from these nanostructures was demonstrated qualitatively in a lift-mode interleave C-AFM study.
A technique to fabricate integrated field emission diodes using silicon nanostructures in a CMOS process technology was developed. The process incorporated the nanostructure growth phase at the closing steps in the process flow. Turn-on voltages as low as ~ 0.6 V were reported for these devices, which make them good candidates for incorporation into standard CMOS circuit applications.
Reproducible I V characteristics exhibited by these fabricated devices were further studied and field emission parameters were extracted. A new consistent and reliable method to extract field emission parameters such as effective barrier height, field conversion factor, and total emitting area at the onset of the field emission regime was developed and is reported herein. The developed parameter extraction method used a unified electron emission approach in the transition region of the device operation. The existence of an electron-supply limited current saturation region at very high electric field was also confirmed.
Both the C-AFM and the device characterization studies were modelled and simulated using the finite element method in COMSOL Multiphysics. The experimental results – the field developed at various operating environments – are explained in relation to these finite element analyses. Field enhancements at the atomically sharp nanostructure apexes as suggested in the experimental studies were confirmed. The nanostructure tip radius effect and sensitivity to small nanostructure height variation were investigated and mathematical relations for the nanostructure regime of our interest were established. A technique to optimize the cathode-opening area was also demonstrated.
Suggestions related to further research on field emission from silicon nanostructures, optimization of the field emission device fabrication process, and fabrication of field emission triodes are elaborated in the final chapter of this thesis. The experimental, modelling, and simulation works of this thesis indicate that silicon field emission devices could be integrated into the existing CMOS process technology. This integration would offer goods from both the worlds of vacuum and solid-sate nanoelectronics – fast ballistic electron transport, temperature insensitivity, radiation hardness, high packing density, mature technological backing, and economies of scale among other features.
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