Enhancement of timing accuracy and waveform quality in high performance ASIC test and verification systems. (1991)
Type of ContentTheses / Dissertations
Thesis DisciplineElectrical Engineering
Degree NameDoctor of Philosophy
PublisherUniversity of Canterbury. Electrical Engineering
AuthorsCharoen, Boonyingshow all
This thesis reviews design, test, and verification aspects of Application-Specific Integrated Circuits (ASIC). A means of improving edge-placement accuracy and waveform quality in high speed, high performance, ASIC test and verification systems has been developed. Its aim is to minimize timing skew, maintain signal integrity at the Device Under Test (DUT), and actively reduce waveform distortions caused by uncertain DUT loading and transmission path imperfections. Frequency Domain Reflectometry (FDR) is used to measure voltage reflection coefficients of both the load (DUT) and Pin Electronic Card (PEC) ends of the transmission path. Time domain waveform is obtained using Discrete Fourier Transformation (DFT). Two prototypes, single and dual directional couplers, have been designed and implemented using Thickfilm-Hybrid Technology (TFH). Both couplers employ strip transmission line structures which support a Transverse Electromagnetic (TEM) propagation mode. FDR experimental results indicate that a matched dual direction.al coupler can be used in such an application, yielding results comparable to those obtained from an automatic network analyzer. The path between the PEC and the DUT is modelled using a signal flow graph (SFG) technique. The model contains both lumped, and distributed circuit elements, each of which is represented by scattering parameters. Load models that represent the DUT or PEC receiver are obtained through a direct search optimization algorithm. This thesis implements two such algorithms, the pattern search and simplex algorithms, based on an example load model. A technique to compute compensation waveforms for linear transmission paths has been developed. Two examples, matched and mismatched channels, are presented. Simulation results show that compensation waveforms computed from the channel characteristic almost completely correct edge-placement timing errors and greatly reduce reflection effects. Implementation of compensation waveforms by simple hardware is possible, leading to edge-placement correction which is almost as good as that obtained from a theoretically computed compensation waveform.