An FPGA Coprocessor for Real-Time Bathymetric Synthetic Aperture Sonar
Thesis DisciplineElectrical Engineering
Degree GrantorUniversity of Canterbury
Degree NameMaster of Engineering
The following is a thesis for a Master's degree in Electrical Engineering. It presents the design of an FPGA coprocessor for real-time bathymetric synthetic aperture sonar. Bathymetry is the process of finding the height of the seafloor; a problem that requires the computation of a large number of short-length correlations and runs slowly on a conventional microprocessor architecture. It is desirable to generate the seafloor bathymetry in real time for use as a visual aid during data gathering, thus the development of a customised coprocessor is required. The design presented utilises the system-on-chip (SoC) approach to FPGA programming, with a microprocessor, memory, communication cores and custom hardware all contained within a single chip. The merits of SoC design are examined and the details of this implementation are presented. The coprocessor communicates with a host computer over a USB link, receiving raw data as it is collected and sending processed data back to be displayed on-screen. The system was successful as a proof-of-concept, capable of processing an eighth of the area imaged by the sonar in real-time. The results for a simulated scene are presented and the performance of the current system examined with a view to improving its capabilities. While further work is required to implement a complete solution to the problem, the work carried out thus far has provided a solid base for future research.