Single parity check product codes and iterative decoding (2001)
Type of ContentTheses / Dissertations
Thesis DisciplineElectrical Engineering
Degree NameDoctor of Philosophy
PublisherUniversity of Canterbury. Electrical and Computer Engineering
AuthorsRankin, David Michaelshow all
The aim of coding theory is to design codes which can achieve the fundamental limits of communication  and yet are simple to implement. On average randomly constructed codes can achieve this goal, but with a decoding complexity that is impractical. Consequently, highly structured codes with practical decoding algorithms have been extensively studied. Unfortunately the vast majority of these codes do not approach capacity. Recent advances involving simple 'random like' codes with practical iterative decoding algorithms have closely approached capacity as the blocklength increases. This thesis investigates single parity check (SPC) product codes and introduces the class of randomly interleaved (RI) SPC product codes. It will be shown that RI SPC product codes can asymptotically force the probability of error to zero, at code rates up to capacity, for almost all codewords. Furthermore the structure of these codes allows a very simple, sub-optimal, iterative decoding algorithm to be used. This thesis also derives an asymptotic analysis on SPC product codes from the decoding point of view. It is shown that the probability of error can be driven to zero, as the blocklength increases, for signal to noise ratios within 2dB of capacity on the additive white Gaussian noise (AWGN) channel. Simulation results for both SPC and RI SPC product codes in an AWGN channel are presented. These results indicate that RI SPC product codes perform very well, typically within 1.5dB of capacity over a wide range of blocklengths and code rates. Further analysis on the weight enumerator of finite length RI SPC product codes is used to confirm the error floor of these codes. Extensions to parallel and serially concatenated SPC product codes are also investigated. Simulation results show an advantageous trade-off between code rate, blocklength and performance for three dimensional parallel concatenated SPC product codes. The design of irregular SPC product codes is also considered, and some simulation results are presented.